Flexible resource access in a microprocessor

ABSTRACT

A superscalar microprocessor defines a hierarchical structure of registers. The top level of the hierarchy includes performance critical registers and pointers to other levels of the hierarchy. A second level of the hierarchy may include special registers. Special registers may include arrays or groups of data. Special registers may be located in a special register file or remotely located throughout the microprocessor. Remote special registers are accessed via a special register bus. Resources throughout the microprocessor are defined as special registers. In this manner, resources throughout the microprocessor are accessed using special register move instructions that are handled in a manner similar to other register moves in instructions. Accordingly, adding and modifying resources within the microprocessor is transparent to the majority of the circuitry of the microprocessor. Thus, the present invention provides a uniform and flexible mechanism of communicating to resources of a microprocessor.

This application is a continuation of U.S. Ser. No. 08/874,031, filedJun. 12, 1997, now U.S. Pat. No. 5,854,912.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to the field of microprocessors and, moreparticularly, to special registers within microprocessors.

2. Description of the Relevant Art

Superscalar microprocessors achieve high performance by executingmultiple instructions per clock cycle and by choosing the shortestpossible clock cycle consistent with the design. As used herein, theterm "clock cycle" refers to an interval of time accorded to variousstages of an instruction processing pipeline within the microprocessor.Storage devices (e.g. registers and arrays) capture their valuesaccording to the clock cycle. For example, a storage device may capturea value according to a rising or falling edge of a clock signal definingthe clock cycle. The storage device then stores the value until thesubsequent rising or falling edge of the clock signal, respectively. Theterm "instruction processing pipeline" is used herein to refer to thelogic circuits employed to process instructions in a pipelined fashion.Although the pipeline may be divided into any number of stages at whichportions of instruction processing are performed, instruction processinggenerally comprises fetching the instruction, decoding the instruction,executing the instruction, and storing the execution results in thedestination identified by the instruction.

Microprocessor designers often design their products in accordance withthe x86 microprocessor architecture in order to take advantage of itswidespread acceptance in the computer industry. Because the x86microprocessor architecture is pervasive, many computer programs arewritten in accordance with the architecture. X86 compatiblemicroprocessors may execute these computer programs, thereby becomingmore attractive to computer system designers who desire x86-compatiblecomputer systems. Such computer systems are often well received withinthe industry due to the wide range of available computer programs.

The x86 microprocessor architecture includes general and specialregisters. General registers are registers that are readily accessibleto all instructions. For example, in the x86 architecture eight generalregisters (EAX, EBX, ECX, EDX EBP, ESI, EDI and ESP) are defined. Thex86 microprocessor architecture also includes special registers. Forexample, the x86 architecture defines six segment registers (CS, SS, DS,ES, FS and GS), a flag register (EFLAGS) and an instruction pointerregister (EIP). In addition, the special registers include a set ofmodel specific registers (MSRs) that may differ between variousimplementations of an x86 microprocessor. For example, a Time StampCounter is not defined as part of the x86 architecture. Someimplementations of an x86 microprocessor, however, include a Time StampCounter as a special register. The Time Stamp Counter may be used tomonitor the performance of a microprocessor. Other examples of specialregister include temporary registers, microcode registers and processorfeature control registers. These registers may be distributed throughoutthe microprocessor.

Resources within a microprocessor include special registers and otherresources such as caches. Access to microprocessor resources istypically accomplished by special instructions. For example, a specialinstruction to flush the instruction cache may be defined. Likewise, aspecial instruction for reading or writing to microcode registers may bedefined. Typically, when new resources are added to a microprocessor,new special instructions are defined to access those resources. Definingnew instructions requires the modification of a significant portion ofthe microprocessor. For example, adding an instruction to flush theinstruction cache may require the modification of the decode unit torecognize the opcode of the new instruction, the modification of themicrocode unit to implement the function of the new instruction, theaddition of signal lines from the microcode unit to the instructioncache to signal the function of the new instruction, and themodification of the instruction cache to receive the signal and executethe function of the new instruction.

The modification of the microprocessor to accommodate new resourcescreates significant design and testing problems. Modifying the circuitryof the microprocessor may introduce debug problems, timing problems andspeed paths. What is desired is a flexible way to access resources thatdoes not require significant redesign to add new resources.

SUMMARY OF THE INVENTION

The problems outlined above are in large part solved by resourceallocation within a microprocessor in accordance with the presentinvention. All resources of a microprocessor are defined as specialregisters. The resources are accessed using instructions that appear assimple register access instructions to the majority of themicroprocessor circuitry. A hierarchical structure of registers isdefined. Performance critical resources reside at the top level of thehierarchy while non-performance critical resources are assigned to lowerlevels of the resource hierarchy. A standardized interface may beconnected to each block of the microprocessor for accessing resourcesdistributed throughout the microprocessor. Accordingly, adding resourcesand communicating to those resources may not require additional controlsignals.

Broadly speaking, the present invention contemplates a microprocessorwith flexible resource access including a decode unit and a specialregister unit. The decode unit decodes a first operand field of aninstruction, wherein the first operand field identifies a primaryregister or a pointer to a plurality of special registers. The specialregister unit is coupled to the decode unit. If the first operand fieldidentifies the pointer to the plurality of special registers, the decodeunit conveys instruction information to the special register unit anddecodes a second operand field. The special register unit then accessesa special register identified by the second operand field.

The present invention further contemplates a method of accessing specialregisters comprising: defining a first register level and a secondregister level, wherein the first register level includes a plurality ofprimary registers and a pointer to a second register level that includesa plurality of special registers; decoding a first operand field of aninstruction, wherein the first operand field identifies one of theplurality of primary registers or the pointer to the second registerlevel; decoding a second operand field of an instruction if the firstoperand field identifies the pointer to the second register level; andaccessing one the plurality of special registers of said second registerlevel identified by the second operand field.

The present invention still further contemplates a microprocessor withflexible resource allocation including: a plurality of special registersincluding one or more remote special registers and one or more localspecial registers; a remote special register bus coupled to the one ormore remote special registers, wherein the remote special registers areaccessed via the remote special register bus; a special register unit iscoupled to the remote special register bus; a decode unit is coupled tothe special register unit, wherein the decode unit routes instructioninformation to the special register unit; the special register unitdecodes the instruction information and accesses a special registeridentified by said instruction information. In this manner, the decodeunit handles an access to a special register in substantially the sameway as an access to a primary register.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the invention will become apparent uponreading the following detailed description and upon reference to theaccompanying drawings in which:

FIG. 1 is a block diagram of one embodiment of a superscalarmicroprocessor.

FIG. 2 is a block diagram of one embodiment of two of the decode unitsshown in FIG. 1.

FIG. 3 is a diagram illustrating the hierarchical structure of resourcesin a microprocessor in accordance with one embodiment of the presentinvention.

FIG. 4 is a block diagram of a portion of a microprocessor involved inthe access of special registers in accordance with one embodiment of thepresent invention.

FIG. 5 is a block diagram of a special register unit in accordance withone embodiment of the present invention.

FIG. 6 is a block diagram illustrating the interconnection of thespecial register bus to portions of a microprocessor in accordance withone embodiment of the present invention.

FIG. 7 is a flow chart illustrating the allocation and access of specialregisters in accordance with one embodiment of the present invention.

FIG. 8A is a diagram of a control word in accordance with one embodimentof the present invention.

FIG. 8B is a diagram of an array locator word in accordance with oneembodiment of the present invention.

FIG. 9 is a block diagram of a computer system including themicroprocessor shown in FIG. 1.

While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof are shown by way ofexample in the drawings and will herein be described in detail. Itshould be understood, however, that the drawings and detaileddescription thereto are not intended to limit the invention to theparticular form disclosed, but on the contrary, the intention is tocover all modifications, equivalents and alternatives falling within thespirit and scope of the present invention as defined by the appendedclaims.

DETAILED DESCRIPTION OF THE INVENTION

Turning now to FIG. 1, a block diagram of one embodiment of amicroprocessor 10 is shown. Microprocessor 10 includes aprefetch/predecode unit 12, a branch prediction unit 14, an instructioncache 16, an instruction alignment unit 18, a plurality of decode units20A-20C, a plurality of reservation stations 22A-22C, a plurality offunctional units 24A-24C, a load/store unit 26, a data cache 28, aregister file 30, a floating point unit 36, a reorder buffer 32, and anMROM unit 34. Blocks referred to herein with a reference number followedby a letter will be collectively referred to by the reference numberalone. For example, decode units 20A-20C will be collectively referredto as decode units 20.

Prefetch/predecode unit 12 is coupled to receive instructions from amain memory subsystem (not shown), and is further coupled to instructioncache 16 and branch prediction unit 14. Similarly, branch predictionunit 14 is coupled to instruction cache 16. Still further, branchprediction unit 14 is coupled to decode units 20 and functional units24. Instruction cache 16 is further coupled to MROM unit 34 andinstruction alignment unit 18. Instruction alignment unit 18 is in turncoupled to decode units 20. Each decode unit 20A-20C is coupled toload/store unit 26 and to respective reservation stations 22A-22C.Reservation stations 22A-22C are further coupled to respectivefunctional units 24A-24C. Additionally, decode units 20 and reservationstations 22 are coupled to register file 30, model specific registerunit 31, and reorder buffer 32. Functional units 24 are coupled toload/store unit 26, register file 30, model specific register unit 31,and reorder buffer 32 as well. Data cache 28 is coupled to load/storeunit 26 and to the main memory subsystem. Finally, MROM unit 34 iscoupled to decode units 20.

Microprocessor 10 is configured to align instructions from instructioncache 16 to decode units 20 using instruction alignment unit 18.Instructions are fetched as an aligned plurality of bytes from a cacheline within instruction cache 16. Instructions of interest may be storedbeginning at any arbitrary byte within the fetched bytes. For example, abranch instruction may be executed having a target address which lieswithin a cache line. The instructions of interest therefore begin at thebyte identified by the target address of the branch instruction. Fromthe instruction bytes fetched, instruction alignment unit 18 identifiesthe instructions to be executed. Instruction alignment unit 18 conveysthe instructions, in predicted program order, to decode units 20 fordecode and execution.

Instruction alignment unit 18 includes a byte queue configured to storeinstruction bytes. An instruction scanning unit within instruction cache16 separates the instructions fetched into instruction blocks. Eachinstruction block comprises a predefined number of instruction bytes.The instruction scanning unit identifies up to a predefined maximumnumber of instructions within the instruction block. Instructionidentification information for each of the identified instructions isconveyed to instruction alignment unit 18 and is stored in the bytequeue. The instruction identification information includes an indicationof the validity of the instruction, as well as indications of the startand end of the instruction within the predefined number of instructionbytes. In one embodiment, the predefined number of instruction bytescomprises eight instruction bytes stored in contiguous main memorystorage locations. The eight instruction bytes are aligned to an eightbyte boundary (i.e. the least significant three bits of the address ofthe first of the contiguous bytes are 0). If more than the maximumnumber of instructions are contained within a particular predefinednumber of instruction bytes, the instruction bytes are scanned againduring a subsequent clock cycle. The same instruction bytes are conveyedas another instruction block, with the additional instructions withinthe instruction bytes identified by the accompanying instructionidentification information. Therefore, an instruction block may bedefined as up to a predefined maximum number of instructions containedwithin a predefined number of instruction bytes.

The byte queue stores each instruction block and correspondinginstruction identification information within a subqueue definedtherein. The subqueues include a position for each possible validinstruction within the instruction block. The positions storeinstruction identification information and are maintained such that theinstruction identification information for the first valid instructionwithin the subqueue is stored in a first position within the subqueue,instruction identification information regarding the second validinstruction (in program order) is stored in a second position within thesubqueue, etc. When instructions within the subqueue are dispatched,instruction identification information corresponding to subsequentinstructions are shifted within the positions of the subqueue such thatthe first of the remaining instructions is stored in the first position.Advantageously, instruction alignment unit 18 may only consider theinstruction information stored in the first position of each subqueue todetect the instruction to be dispatched to decode unit 20A. Similarly,only the second position of the first subqueue (the subqueue storinginstructions prior to the instructions stored in the other subqueues inprogram order) may be considered for dispatch of instructions to decodeunit 20B. By managing the subqueues in this manner, logic for selectingand aligning instructions may be simplified. Fewer cascaded levels oflogic may be employed for performing the selection and alignmentprocess, allowing for high frequency implementation of microprocessor10.

Because instructions are variable length, an instruction may beginwithin a particular instruction block but end in another instructionblock. Instructions beginning within a particular instruction block andending in another instruction block are referred to as "overflowinstructions". The subqueue storing the instruction block within whichan overflow instruction begins uses the last position to store theoverflow instruction's identification information. Unlike the otherpositions, the instruction identification information of the lastposition is not shifted from the last position when an overflowinstruction is stored therein. Advantageously, instruction alignmentunit 18 need only search the last position of a particular subqueue toidentify an instruction overflowing from one subqueue to another.

As used herein, the term queue refers to a storage device for storing aplurality of data items. The data items are stored with an orderedrelationship between them. For example, the data items of the byte queueare instructions. The ordered relationship between the instructions isthe program order of the instructions. Data items are removed from thequeue according to the ordered relationship in a first in-first out(FIFO) fashion. Additionally, the term shifting is used to refer tomovement of data items within the queue. When a data item is shiftedfrom a first storage location to a second storage location, the dataitem is copied from the first storage location to the second storagelocation and invalidated in the second storage location. Theinvalidation may occur by shifting yet another data item into the secondstorage location, or by resetting a valid indication in the secondstorage location.

Instruction cache 16 is a high speed cache memory provided to storeinstructions. Instructions are fetched from instruction cache 16 anddispatched to decode units 20. In one embodiment, instruction cache 16is configured to store up to 32 kilobytes of instructions in an 8 wayset associative structure having 32 byte lines (a byte comprises 8binary bits). Instruction cache 16 may additionally employ a wayprediction scheme in order to speed access times to the instructioncache. Instead of accessing tags identifying each line of instructionsand comparing the tags to the fetch address to select a way, instructioncache 16 predicts the way that is accessed. In this manner, the way isselected prior to accessing the instruction storage. The access time ofinstruction cache 16 may be similar to a direct-mapped cache. A tagcomparison is performed and, if the way prediction is incorrect, thecorrect instructions are fetched and the incorrect instructions arediscarded. It is noted that instruction cache 16 may be implemented as afully associative, set associative, or direct mapped configuration.

Instructions are fetched from main memory and stored into instructioncache 16 by prefetch/predecode unit 12. Instructions may be prefetchedprior to instruction cache 16 recording a miss for the instructions inaccordance with a prefetch scheme. A variety of prefetch schemes may beemployed by prefetch/predecode unit 12. As prefetch/predecode unit 12transfers instructions from main memory to instruction cache 16,prefetch/predecode unit 12 generates three predecode bits for each byteof the instructions: a start bit, an end bit, and a functional bit. Thepredecode bits form tags indicative of the boundaries of eachinstruction. The predecode tags may also convey additional informationsuch as whether a given instruction can be decoded directly by decodeunits 20 or whether the instruction is executed by invoking a microcodeprocedure controlled by MROM unit 34, as will be described in greaterdetail below. Still further, prefetch/predecode unit 12 may beconfigured to detect branch instructions and to store branch predictioninformation corresponding to the branch instructions into branchprediction unit 14.

One encoding of the predecode tags for an embodiment of microprocessor10 employing the x86 instruction set will next be described. If a givenbyte is the first byte of an instruction, the start bit for that byte isset. If the byte is the last byte of an instruction, the end bit forthat byte is set. For this embodiment of microprocessor 10, instructionswhich may be directly decoded by decode units 20 are referred to as"fast path" instructions. Fast path instructions may be an example ofdirectly-decoded instructions for this embodiment. The remaining x86instructions are referred to as MROM instructions, according to oneembodiment. For this embodiment, MROM instructions are an example ofmicrocode instructions.

For fast path instructions, the functional bit is set for each prefixbyte included in the instruction, and cleared for other bytes.Alternatively, for MROM instructions, the functional bit is cleared foreach prefix byte and set for other bytes. The type of instruction may bedetermined by examining the functional bit corresponding to the endbyte. If that functional bit is clear, the instruction is a fast pathinstruction. Conversely, if that functional bit is set, the instructionis an MROM instruction. The opcode of an instruction may thereby belocated within an instruction which may be directly decoded by decodeunits 20 as the byte associated with the first clear functional bit inthe instruction. For example, a fast path instruction including twoprefix bytes, a Mod R/M byte, and an SIB byte would have start, end, andfunctional bits as follows:

    ______________________________________                                        Start bits     10000                                                          End bits       00001                                                          Functional bits                                                                              11000                                                          ______________________________________                                    

MROM instructions are instructions which are determined to be toocomplex for decode by decode units 20. MROM instructions are executed byinvoking MROM unit 34. More specifically, when an MROM instruction isencountered, MROM unit 34 parses and issues the instruction into asubset of defined fast path instructions to effectuate the desiredoperation. MROM unit 34 dispatches the subset of fast path instructionsto decode units 20. A listing of exemplary x86 instructions categorizedas fast path instructions will be provided further below.

Microprocessor 10 employs branch prediction in order to speculativelyfetch instructions subsequent to conditional branch instructions. Branchprediction unit 14 is included to perform branch prediction operations.In one embodiment, up to two branch target addresses are stored withrespect to each cache line in instruction cache 16. Prefetch/predecodeunit 12 determines initial branch targets when a particular line ispredecoded. Subsequent updates to the branch targets corresponding to acache line may occur due to the execution of instructions within thecache line. Instruction cache 16 provides an indication of theinstruction address being fetched, so that branch prediction unit 14 maydetermine which branch target addresses to select for forming a branchprediction. Decode units 20 and functional units 24 provide updateinformation to branch prediction unit 14. Because branch prediction unit14 stores two targets per cache line, some branch instructions withinthe line may not be stored in branch prediction unit 14. Decode units 20detect branch instructions which were not predicted by branch predictionunit 14. Functional units 24 execute the branch instructions anddetermine if the predicted branch direction is incorrect. The branchdirection may be "taken", in which subsequent instructions are fetchedfrom the target address of the branch instruction. Conversely, thebranch direction may be "not taken", in which subsequent instructionsare fetched from memory locations consecutive to the branch instruction.When a mispredicted branch instruction is detected, instructionssubsequent to the mispredicted branch are discarded from the variousunits of microprocessor 10. A variety of suitable branch predictionalgorithms may be employed by branch prediction unit 14.

Instructions fetched from instruction cache 16 are conveyed toinstruction alignment unit 18. As instructions are fetched frominstruction cache 16, the corresponding predecode data is scanned toprovide information to instruction alignment unit 18 (and to MROM unit34) regarding the instructions being fetched. Instruction alignment unit18 utilizes the scanning data to align an instruction to each of decodeunits 20. In one embodiment, instruction alignment unit 18 alignsinstructions from three sets of eight instruction bytes to decode units20. Decode unit 20A receives an instruction which is prior toinstructions concurrently received by decode units 20B and 20C (inprogram order). Similarly, decode unit 20B receives an instruction whichis prior to the instruction concurrently received by decode unit 20C inprogram order. As used herein, the term "program order" refers to theorder of the instruction as coded in the original sequence in memory.The program order of instructions is the order in which the instructionswould be executed upon a microprocessor which fetches, decodes,executes, and writes the result of a particular instruction prior tofetching another instruction. Additionally, the term "dispatch" is usedto refer to conveyance of an instruction to an issue position which isto execute the instruction. Issue positions may also dispatch load/storememory operations to load/store unit 26.

Decode units 20 are configured to decode instructions received frominstruction alignment unit 18. Register operand information is detectedand routed to register file 30, MSR unit 31, and reorder buffer 32.Additionally, if the instructions require one or more memory operationsto be performed, decode units 20 dispatch the memory operations toload/store unit 26. Each instruction is decoded into a set of controlvalues for functional units 24, and these control values are dispatchedto reservation stations 22 along with operand address information anddisplacement or immediate data which may be included with theinstruction.

Microprocessor 10 supports out of order execution, and thus employsreorder buffer 32 to keep track of the original program sequence forregister read and write operations, to implement register renaming, toallow for speculative instruction execution and branch mispredictionrecovery, and to facilitate precise exceptions. A temporary storagelocation within reorder buffer 32 is reserved upon decode of aninstruction that involves the update of a register to thereby storespeculative register states. If a branch prediction is incorrect, theresults of speculatively-executed instructions along the mispredictedpath can be invalidated in the buffer before they are written toregister file 30. Similarly, if a particular instruction causes anexception, instructions subsequent to the particular instruction may bediscarded. In this manner, exceptions are "precise" (i.e. instructionssubsequent to the particular instruction causing the exception are notcompleted prior to the exception). It is noted that a particularinstruction is speculatively executed if it is executed prior toinstructions which precede the particular instruction in program order.Preceding instructions may be a branch instruction or anexception-causing instruction, in which case the speculative results maybe discarded by reorder buffer 32.

The instruction control values and immediate or displacement dataprovided at the outputs of decode units 20 are routed directly torespective reservation stations 22. In one embodiment, each reservationstation 22 is capable of holding instruction information (i.e.,instruction control values as well as operand values, operand tagsand/or immediate data) for up to three pending instructions awaitingissue to the corresponding functional unit. It is noted that for theembodiment of FIG. 1, each reservation station 22 is associated with adedicated functional unit 24. Accordingly, three dedicated "issuepositions" are formed by reservation stations 22 and functional units24. In other words, issue position 0 is formed by reservation station22A and functional unit 24A. Instructions aligned and dispatched toreservation station 22A are executed by functional unit 24A. Similarly,issue position 1 is formed by reservation station 22B and functionalunit 24B; and issue position 2 is formed by reservation station 22C andfunctional unit 24C. As used herein, the term "issue position" refers tologic circuitry configured to receive an instruction and to execute thatinstruction. Once the instruction enters the issue position, it remainsin that issue position until the execution of the instruction iscompleted.

Upon decode of a particular instruction, if a required operand is ageneral register location, register address information is routed toreorder buffer 32 and register file 30 simultaneously. Those of skill inthe art will appreciate that the x86 register file includes eight 32 bitgeneral registers (i.e., typically referred to as EAX, EBX, ECX, EDX,EBP, ESI, EDI and ESP). In embodiments of microprocessor 10 which employthe x86 microprocessor architecture, register file 30 comprises storagelocations for each of the 32 bit real registers. Additional storagelocations may be included within register file 30 for use by otherblocks of microprocessor 10. Reorder buffer 32 contains temporarystorage locations for results which change the contents of theseregisters to thereby allow out of order execution. A temporary storagelocation of reorder buffer 32 is reserved for each instruction which,upon decode, is determined to modify the contents of one of the realregisters. Therefore, at various points during execution of a particularprogram, reorder buffer 32 may have one or more locations which containthe speculatively executed contents of a given register. If followingdecode of a given instruction it is determined that reorder buffer 32has a previous location or locations assigned to a register used as anoperand in the given instruction, the reorder buffer 32 forwards to thecorresponding reservation station either: 1) the value in the mostrecently assigned location, or 2) a tag for the most recently assignedlocation if the value has not yet been produced by the functional unitthat will eventually execute the previous instruction. If reorder buffer32 has a location reserved for a given register, the operand value (orreorder buffer tag) is provided from reorder buffer 32 rather than fromregister file 30. If there is no location reserved for a requiredregister in reorder buffer 32, the value is taken directly from registerfile 30. If the operand corresponds to a memory location, the operandvalue is provided to the reservation station through load/store unit 26.

In one particular embodiment, reorder buffer 32 is configured to storeand manipulate concurrently decoded instructions as a unit. Thisconfiguration will be referred to herein as "line-oriented". Bymanipulating several instructions together, the hardware employed withinreorder buffer 32 may be simplified. For example, a line-orientedreorder buffer included in the present embodiment allocates storagesufficient for instruction information pertaining to three instructions(one from each decode unit 20) whenever one or more instructions aredispatched by decode units 20. By contrast, a variable amount of storageis allocated in conventional reorder buffers, dependent upon the numberof instructions actually dispatched. A comparatively larger number oflogic gates may be required to allocate the variable amount of storage.When each of the concurrently decoded instructions has executed, theinstruction results are stored into register file 30 simultaneously. Thestorage is then free for allocation to another set of concurrentlydecoded instructions. Additionally, the amount of control logiccircuitry employed per instruction is reduced because the control logicis amortized over several concurrently decoded instructions. A reorderbuffer tag identifying a particular instruction may be divided into twofields: a line tag and an offset tag. The line tag identifies the set ofconcurrently decoded instructions including the particular instruction,and the offset tag identifies which instruction within the setcorresponds to the particular instruction. It is noted that storinginstruction results into register file 30 and freeing the correspondingstorage is referred to as "retiring" the instructions. It is furthernoted that any reorder buffer configuration may be employed in variousembodiments of microprocessor 10.

As noted earlier, reservation stations 22 store instructions until theinstructions are executed by the corresponding functional unit 24. Aninstruction is selected for execution if: (i) the operands of theinstruction have been provided; and (ii) the operands have not yet beenprovided for instructions which are within the same reservation station22A-22C and which are prior to the instruction in program order. It isnoted that when an instruction is executed by one of the functionalunits 24, the result of that instruction is passed directly to anyreservation stations 22 that are waiting for that result at the sametime the result is passed to update reorder buffer 32 (this technique iscommonly referred to as "result forwarding"). An instruction may beselected for execution and passed to a functional unit 24A-24C duringthe clock cycle that the associated result is forwarded. Reservationstations 22 route the forwarded result to the functional unit 24 in thiscase.

In one embodiment, each of the functional units 24 is configured toperform integer arithmetic operations of addition and subtraction, aswell as shifts, rotates, logical operations, and branch operations. Theoperations are performed in response to the control values decoded for aparticular instruction by decode units 20. It is noted that a floatingpoint unit (not shown) may also be employed to accommodate floatingpoint operations. The floating point unit may be operated similar toload/store unit 26 in that any of decode units 20 may dispatchinstructions to the floating point unit. Additionally, functional units24 may be configured to perform address generation for load and storememory operations performed by load/store unit 26.

Each of the functional units 24 also provides information regarding theexecution of conditional branch instructions to the branch predictionunit 14. If a branch prediction was incorrect, branch prediction unit 14flushes instructions subsequent to the mispredicted branch that haveentered the instruction processing pipeline, and causes fetch of therequired instructions from instruction cache 16 or main memory. It isnoted that in such situations, results of instructions in the originalprogram sequence which occur after the mispredicted branch instructionare discarded, including those which were speculatively executed andtemporarily stored in load/store unit 26 and reorder buffer 32.

Results produced by functional units 24 are sent to reorder buffer 32 ifa general register value is being updated and to load/store unit 26 ifthe contents of a memory location are changed. If the result is to bestored in a general register, reorder buffer 32 stores the result in thelocation reserved for the value of the register when the instruction wasdecoded. A plurality of result buses 38 are included for forwarding ofresults from functional units 24 and load/store unit 26. Result buses 38convey the result generated, as well as the reorder buffer tagidentifying the instruction being executed.

Load/store unit 26 provides an interface between functional units 24 anddata cache 28. In one embodiment, load/store unit 26 is configured witha load/store buffer having eight storage locations for data and addressinformation for pending loads or stores. Decode units 20 arbitrate foraccess to the load/store unit 26. When the buffer is full, a decode unitmust wait until load/store unit 26 has room for the pending load orstore request information. Load/store unit 26 also performs dependencychecking for load memory operations against pending store memoryoperations to ensure that data coherency is maintained. A memoryoperation is a transfer of data between microprocessor 10 and the mainmemory subsystem. Memory operations may be the result of an instructionwhich utilizes an operand stored in memory, or may be the result of aload/store instruction which causes the data transfer but no otheroperation. Additionally, load/store unit 26 may include a specialregister storage for special registers such as the segment registers andother registers related to the address translation mechanism defined bythe x86 microprocessor architecture.

In one embodiment, load/store unit 26 is configured to perform loadmemory operations speculatively. Store memory operations are performedin program order, but may be speculatively stored into the predictedway. If the predicted way is incorrect, the data prior to the storememory operation is subsequently restored to the predicted way and thestore memory operation is performed to the correct way. In anotherembodiment, stores may be executed speculatively as well. Speculativelyexecuted stores are placed into an store buffer, along with a copy ofthe cache line prior to the update. If the speculatively executed storeis later discarded due to branch misprediction or exception, the cacheline may be restored to the value stored in the buffer. It is noted thatload/store unit 26 may be configured to perform any amount ofspeculative execution, including no speculative execution.

Data cache 28 is a high speed cache memory provided to temporarily storedata being transferred between load/store unit 26 and the main memorysubsystem. In one embodiment, data cache 28 has a capacity of storing upto sixteen kilobytes of data in an eight way set associative structure.Similar to instruction cache 16, data cache 28 may employ a wayprediction mechanism. It is understood that data cache 28 may beimplemented in a variety of specific memory configurations, including aset associative configuration.

In one particular embodiment of microprocessor 10 employing the x86microprocessor architecture, instruction cache 16 and data cache 28 arelinearly addressed. The linear address is formed from the offsetspecified by the instruction and the base address specified by thesegment portion of the x86 address translation mechanism. Linearaddresses may optionally be translated to physical addresses foraccessing a main memory. The linear to physical translation is specifiedby the paging portion of the x86 address translation mechanism. It isnoted that a linear addressed cache stores linear address tags. A set ofphysical tags (not shown) may be employed for mapping the linearaddresses to physical addresses and for detecting translation aliases.Additionally, the physical tag block may perform linear to physicaladdress translation.

Turning now to FIG. 2, a block diagram of one embodiment of decode units20B and 20C are shown. Each decode unit 20 receives an instruction frominstruction alignment unit 18. Additionally, MROM unit 34 is coupled toeach decode unit 20 for dispatching fast path instructions correspondingto a particular MROM instruction. Decode unit 20B comprises early decodeunit 40B, multiplexer 42B, and opcode decode unit 44B. Similarly, decodeunit 20C includes early decode unit 40C, multiplexer 42C, and opcodedecode unit 44C.

Certain instructions in the x86 instruction set are both fairlycomplicated and frequently used. In one embodiment of microprocessor 10,such instructions include more complex operations than the hardwareincluded within a particular functional unit 24A-24C is configured toperform. Such instructions are classified as a special type of MROMinstruction referred to as a "double dispatch" instruction. Theseinstructions are dispatched to a pair of opcode decode units 44. It isnoted that opcode decode units 44 are coupled to respective reservationstations 22. Each of opcode decode units 44A-44C forms an issue positionwith the corresponding reservation station 22A-22C and functional unit24A-24C. Instructions are passed from an opcode decode unit 44 to thecorresponding reservation station 22 and further to the correspondingfunctional unit 24.

Multiplexer 42B is included for selecting between the instructionsprovided by MROM unit 34 and by early decode unit 40B. During times inwhich MROM unit 34 is dispatching instructions, multiplexer 42B selectsinstructions provided by MROM unit 34. At other times, multiplexer 42Bselects instructions provided by early decode unit 40B. Similarly,multiplexer 42C selects between instructions provided by MROM unit 34,early decode unit 40B, and early decode unit 40C. The instruction fromMROM unit 34 is selected during times in which MROM unit 34 isdispatching instructions. During times in which early decode unit 40Bdetects a double dispatch instruction, the instruction from early decodeunit 40B is selected by multiplexer 42C. Otherwise, the instruction fromearly decode unit 40C is selected. Selecting the instruction from earlydecode unit 40B into opcode decode unit 44C allows a fast pathinstruction decoded by decode unit 20B to be dispatched concurrentlywith a double dispatch instruction decoded by decode unit 20A.

According to one embodiment employing the x86 instruction set, earlydecode units 40 perform the following operations:

(i) merge the prefix bytes of the instruction into an encoded prefixbyte;

(ii) decode unconditional branch instructions (which may include theunconditional jump, the CALL, and the RETURN) which were not detectedduring branch prediction;

(iii) decode source and destination flags;

(iv) decode the source and destination operands which are registeroperands and generate operand size information; and

(v) determine the displacement and/or immediate size so thatdisplacement and immediate data may be routed to the opcode decode unit.

Opcode decode units 44 are configured to decode the opcode of theinstruction, producing control values for functional unit 24.Displacement and immediate data are routed with the control values toreservation stations 22.

Since early decode units 40 detect operands, the outputs of multiplexers42 are routed to register file 30, MSR file 31, and reorder buffer 32.Operand values or tags may thereby be routed to reservation stations 22.Additionally, memory operands are detected by early decode units 40.Therefore, the outputs of multiplexers 42 are routed to load/store unit26. Memory operations corresponding to instructions having memoryoperands are stored by load/store unit 26.

Turning now to FIG. 3, a diagram illustrating one embodiment of ahierarchical structure of resources within a microprocessor is shown.The hierarchy of FIG. 3 is for illustrative purposes only, otherprocessors may utilize other hierarchical structures. The hierarchyincludes several register levels. At the top level of the hierarchy is aplurality of primary registers. The primary registers may includeperformance critical resources such as general registers, segmentregisters, a flag register and an instruction pointer register. Inaddition, the top level of the hierarchy includes a special registerpointer and a floating point register pointer. Each pointer identifies asecond level of the register hierarchy. For example, the top level ofthe register hierarchy may include 64 primary register addresses. Of the64 primary register addresses, 62 addresses may identify primaryregisters. One of the primary register addresses is a pointer to aspecial register hierarchical level. Another primary register address isa pointer to a floating point register hierarchical level.

In one embodiment, the primary registers are identified directly in theregister operand fields of an instruction. The term register operandfield identifies an operand field that normally identifies a source ordestination register. Generally speaking, an operand field is a portionof an instruction that identifies parameters of an instruction, e.g.,source register, destination register, memory address, immediate data ordisplacement data.

To access a special register, a first register operand field specifiesthe special register pointer and another operand field, or a register,identifies which special register to access. For example, the specialregister may be identified by the immediate field of an instruction.Alternatively, a general register or a temporary register may store avalue that identifies the special register. Likewise, when a floatingpoint register is accessed, a first operand field identifies thefloating point register pointer and another operand field, or register,specifies which floating point register to access.

In one embodiment, the special registers are split between local specialregisters and remote special registers. The more time critical resources(but not as time critical as the primary registers) are allocated to thelocal special registers. In one embodiment, the local special registersare located in a special register file. The less time critical specialregisters are allocated to the remote special registers and may belocated throughout the microprocessor. Remote special registers mayinclude arrays, groups or multiples of data. For example, a data cachemay be defined as a remote special register. An operand field or aregister identifies which element of the array to access. In oneembodiment, remote special registers are accessed via a remote specialregister bus 414. The hierarchical structure discussed above may beextended to include more levels of the hierarchy and/or to include morebranches of the hierarchy.

The following instructions illustrate one method of defininginstructions to access registers of the hierarchical register structureillustrated in FIG. 3. The following instruction moves data from a localspecial register DS segment base to primary register tmp0:

MOV tmp0, SR, (srctl=read, ds₋₋ base).

The MOV instruction includes three operand fields: two register operandfields and an immediate field. The first operand field specifies thedestination register of the move instruction. In the illustratedembodiment, primary register tmp0 is the destination register. Thesecond operand field specifies the source register of the moveinstruction. In the illustrated embodiment, the second instructionoperand does not specify a primary register, but rather specifies apointer to the special registers. The immediate field of the instructiondefines which special register to access and the type of operation toperform on the special register. The immediate field specifies that aread operation is to be performed and specifies the special register asthe DS segment base register (ds₋₋ base). To most portions of themicroprocessor, this instruction appears as a normal register moveinstruction.

The following pair of instructions illustrates one method of accessingan array such as a data cache array:

MOV SR, tmp1, (srctl=write, array locator word)

MOV temp0, SR, (srctl=array read, dc₋₋ data)

In the illustrated embodiment, accessing an element of the data cachearray requires two instructions. The first instruction moves data, whichidentifies the element of the array to access, from general registertmp1 to a special register called an array locator word. Thisinstruction is the same format as the move instruction discussed above.The array locator word is a special register that stores dataidentifying the element of the array. The second instruction moves theelement of a data array to primary register temp0. The first operandfield of the move instruction specifies the destination register, thesecond operand field contains a pointer to the special register, and theimmediate field specifies the operation as an array read and identifiesthe special register as the data cache array. As noted above, theimmediate field contains data identifying the special register to accessand the type of bus operation. When an instruction that accesses anarray is encountered, the array locator word is read to determine whichelement of the array to access.

The operations, or bus operations, defined in the immediate fieldinclude read operations, write operations, array read operations, arraywrite operations, and array invalidate operations. In other embodiments,other bus operations may be defined. The immediate field also identifiesthe special register to be accessed. For example, if the specialregister space includes 256 special registers, then an 8-bit addressfield is used. Each address identifies a unique special register.

Turning now to FIG. 4, portions of a microprocessor that relate to theaccess of special registers according to one embodiment of the presentinvention is shown. The portions of the microprocessor includeinstruction alignment unit 18, decode unit 20, reservations stations 22,functional unit 24, MROM unit 34, load/store unit 26 and reorder buffer32. Outputs of MROM unit 34 and instruction alignment unit 18 areprovided to decode unit 20. Decode unit 20 is coupled to reservationstation 22, load/store unit 26 and reorder buffer 32. Reservationstation 22 is additionally coupled to functional unit 24. Functionalunit 24 is coupled to reorder buffer 32 and load/store unit 26.Load/store unit 26 is coupled to reorder buffer 32.

Special register instructions may be either MROM instructions or fastpath instructions. As noted above, MROM instructions are conveyed toMROM unit 34, which parses the instruction into a subset of fast pathinstructions. The fast path instructions are dispatched from MROM unit34 to decode unit 20. Alternatively, fast path special registerinstructions are dispatched directly from instruction alignment unit 18to decode unit 20. Special register access instructions received bydecode unit 20 are handled in a similar manner whether received fromMROM unit 34 or instruction alignment unit 18.

In the illustrated embodiment, the special register unit 202 is locatedwithin load/store unit 26. Special register unit 202 stores the localspecial registers which may include the segment registers. Because, inone embodiment, the load/store unit performs most of the segmentregister operations, special register unit 202 is located withinload/store unit 26. In other embodiments, special register unit 202 maybe located in other portions of microprocessor 10. Load/store unit 26may control access to both local special registers and remote specialregisters. In one embodiment, special register unit 202 includes a localregister file for storing local special registers. In one particularembodiment, remote special registers are located in other blocks of themicroprocessor and are accessed via a remote special register bus 414.

Upon decode of a special register access instruction, decode unit 20conveys instruction information to load/store unit 26. Instructioninformation may include operand and control data. In the illustratedembodiment, operand data is conveyed on op bus 410 and control data isconveyed on control bus 408. The control data includes the type of busoperation and data identifying a special register. In one embodiment,the control data is the same data as the immediate field of theinstruction. The operand data may indicate, among other things, theoperand of the instruction.

Decode unit 20 additionally conveys an operand request signal to reorderbuffer 32 on operand request bus 412. In one embodiment, when reorderbuffer 32 receives an operand request signal, it allocates a storagelocation within reorder buffer 32 for the instruction. Reorder buffer 32outputs the reorder buffer tag, which identifies the storage locationallocated to the instruction, on the reorder buffer tag bus 402. Reorderbuffer 32 also performs a dependency check on the operands of theinstruction with operands of previous instructions. If the sourceoperand of an instruction is the destination operand of a previousinstruction, a dependency exists. If the previous instruction on whichthe current instruction depends has returned a result, the reorderbuffer outputs the result on the operand tag bus 404. If the previousinstruction has not returned a result, the reorder buffer returns thereorder buffer tag of the previous instruction on operand tag bus 404.As discussed above, the operand tag is used by load/store unit 26 tocapture the general register result from the result bus 38. Theload/store unit conveys special register results to reorder buffer 32via a load/store result bus 406.

In one embodiment, the transfer of data between general registers andspecial registers is performed by reorder buffer 32 and load/store unit26. General register data is passed directly from reorder buffer 32 toload/store unit 26. Special register data is passed directly fromload/store unit 26 to reorder buffer 32. The special registerinstruction is retired in reorder buffer 32. In this embodiment,reservation station 22 and functional unit 24 are not involved in thetransfer of data between a primary register and a special register. Inan alternative embodiment, decode unit 20 additionally passesinstruction information to reservation station 22. Special register datais conveyed from load/store unit 26 to reservation station 22. Whenreservation station 22 receives the operand data from load/store unit26, reservation station 22 conveys the instruction and the operand datato functional unit 24. Functional unit 24 conveys the special registerdata to reorder buffer 32 via result bus 38. In this embodiment,load/store result bus 406 is coupled to reservation station 22.

For illustrative purposes, a move instruction from a special register toa general register is discussed. When decode unit 20 encounters a moveinstruction from a special register to a general register, it asserts anoperand request signal to reorder buffer 32 on operand request bus 412.Reorder buffer 32 allocates a storage location for the instructionresult and outputs the reorder buffer tag of the allocated storagelocation to load/store unit 26. Load/store unit 26 additionally receivescontrol data from decode unit 20. The control data indicates the busoperation is a read operation and identifies the source specialregister. Load/store unit 26 reads the special register identified bythe control signal. If the special register is a local special register,the value stored in the special register is read from special registerunit 202. If the special register is a remote special register,load/store unit 26 reads the value stored in the remote special registervia the remote special register bus 414. Accessing special registerswithin load/store unit 26 is discussed in more detail below in referenceto FIG. 5. Load/store unit 26 outputs the value read from the specialregister and the reorder buffer tag allocated to the instruction onload/store result bus 406. Reorder buffer 32 receives the specialregister value and stores it in the storage location allocated for thatresult.

In one particular embodiment, reorder buffer 32 is a line orientedreorder buffer. In this embodiment, the reorder tag output from thereorder buffer to the load/store unit and the result output fromload/store unit 26 to reorder buffer 32 specifies both the line andoffset within the line oriented reorder buffer.

A move instruction from a general register to a special register isdiscussed next. When decode unit 20 encounters a move instruction from ageneral register to a special register, decode unit 20 outputs anoperand request signal to reorder buffer 32 and conveys control dataidentifying the type of bus operation and the special register toload/store unit 26. In response to the operand request signal, reorderbuffer 32 performs dependency checks on the source register. Asdiscussed above, if the source register does not depend on any previousinstructions, reorder buffer 32 returns the source register value onoperand tag bus 404. Load/store unit 26 stores the source register tothe special register identified by the control signal. If, however, thesource register depends upon the result of another instruction, reorderbuffer 32 returns the tag of the instruction on which the sourceregister depends on operand tag bus 404. Load/store unit 26 monitorsresult bus 38 to capture the source operand when it becomes available.When load/store unit 26 captures the source operand, it stores thesource operand to the special register designated by the control signal.If the special register is a local special register, the source operandis stored in special register unit 202. If the special register is aremote special register, the source operand is stored to the remotespecial register via the remote special register bus 414. Storing datato local and remote special registers is discussed in more detail belowin reference to FIG. 5.

Turning now to FIG. 5, a block diagram of one embodiment of a specialregister unit 202 is shown. Special register unit 202 includes buffer302, control 304, local register file 306, special register businterface 308 and result bus control 310. Buffer 302 receives operand,control and tag data from decode unit 20 and reorder buffer 32. Buffer302 is a storage device for storing pending special register accessinstructions. In one embodiment, buffer 302 is a first-in-first-out(FIFO) storage device. Read operations may be issued for execution afterthe operation and control information is available. Write instructionsmay be issued for execution after the operands have been captured fromresult bus 38. In one particular embodiment, buffer 302 acts as areservation station and allows for non-sequential execution of readoperations. All write operations are executed in sequence while readoperations can be executed out of sequence as long as there are no writeoperations to the same special register pending ahead of the readoperation in buffer 302. Buffer 302 issues instructions for execution tocontrol 304. Control 304 determines whether the instruction accesses alocal special register or a remote special register. Access may beeither a read or write operation. If a local special register isaccessed, control 304 accesses the local special register from localregister file 306. If the instruction accesses a remote specialregister, control 304 passes control and operand information to specialregister bus interface 308. Special register bus interface 308 reads orwrites to a special register via remote special register bus 414. Theregister values read during a read operation are passed from localregister file 306 or special register bus interface 308 to result buscontrol 310. Result bus control 310 outputs the register values onload/store result bus 406. Result bus control 310 additionally outputsthe tag associated with the read instruction on load/store result bus406. As discussed above, reorder buffer 32 is coupled to load/storeresult bus 406. Reorder buffer 32 uses the data from load/store resultbus 406 to store the register value in the storage location allocated toa special register read instruction.

Turning now to FIG. 6, a block diagram illustrating the interconnectionof remote special register bus 414 to portions of microprocessor 10according to one embodiment of the present invention is shown. In theillustrated embodiment, remote special register bus 414 is coupled toload/store unit 26, instruction cache 16, data cache 28, functionalunits 24, reorder buffer 32 and MROM unit 34. As discussed above,special registers may be located throughout microprocessor 10. In oneembodiment, special registers located in portions of microprocessor 10other than load/store unit 26 are accessed via remote special registerbus 414. Remote special register bus 414 provides a standardizedinterface for communicating between the blocks of the microprocessor.

Additional special registers may be defined without redesigning oradding additional signals to the microprocessor. For example, adding anew special register to instruction cache 16 does not require anyadditional control signals to be routed from load/store unit 26 toinstruction cache 16. Instruction cache 16 is already coupled to remotespecial register bus 414. Instruction cache 16 is modified to receive oroutput data on remote special register bus 414 when the new remoteregister is addressed. Additionally, new functions or commands can beadded without modifying other portions of the microprocessor. Forexample, to add a flush instruction cache command, a new specialregister within instruction cache 16 may be defined. Writing aparticular data value to the special register may initiate the flushcommand. Alternatively, an existing special register in cache 16 mayreceive the sequence that initiates the flush command. In either case,only instruction cache 16 needs to be modified to add the new command.Decode unit 20 treats all moves to special registers in the same manner.Likewise, remote special register bus 414 treats all transfers tospecial registers in the same manner. If an existing special register isused, only the data being transferred to instruction cache 16 differs.If a new special register is defined, remote special register bus 414outputs a new address. Remote special register bus 414 may implement anyconventional protocol for transferring data between portions of acircuit.

Turning now to FIG. 7, a flow chart diagram illustrating the access of aresource according to one embodiment of the present invention is shown.In step 702, a first register level and a second register level isdefined. In one embodiment, more time critical registers are allocatedto the first register level and less time critical registers areallocated to the second register level. In step 704, a first operandfield of an instruction is decoded. In one embodiment, the first operandfield identifies either a register allocated to the first register levelor a pointer to the second register level. In decisional step 706, it isdetermined whether the operand field identifies a special registerpointer. If the operand field does identify a special register pointer,then in step 708, a second operand field is decoded. The second operandfield identifies which of the registers allocated to the second registerlevel to access. In step 710, the register identified by the secondoperand field is accessed. If in decisional step 706, the first operandfield does not specify a special register pointer, then in step 712, theprimary register identified by the first operand field is accessed. Inother embodiments, the first register level may include more than onepointer. For example, the first register level may include a pointer tofloating point registers in addition to special registers. In thisalternative embodiment, if the first operand field identifies thefloating register pointer, then the second operand field is decoded todetermine which floating point operand to access.

FIG. 8A illustrates a command word output on the special register busaccording to one embodiment of the present invention. The command wordidentifies a type of bus operation and an address of a special register.In the illustrated embodiment, the operation field is 4-bits and thusmay specify 16 bus operations. For example, the operation field mayindicate that the bus operation is a read from a special register, awrite to a special register, an array read, an array write, or an arrayinvalidate. The address field is 8-bits and thus may specify up to 256special registers.

FIG. 8B illustrates an array locator word according to one embodiment ofthe present invention. As discussed above, when an array is accessed,the array locator word indicates the element of the array to access. Inthe illustrated embodiment, the array locator word includes a typefield, an op field, a way field and an index field. The type fielddefines a subarray within the array addressed by the command word. Forexample, the tag field may identify a data array, a tag array, apredecode array, a way prediction array, or a prefetch buffer array.Other subarrays may be defined in other implementations of amicroprocessor. The op field definition depends on the command word. Forexample, when an array is invalidated, the op field defines the type ofinvalidation. For example, the op field may identify a globalinvalidate, a line invalidate or a line invalidate based on date. Theway field selects one of the ways in the array. The index field containsthe row and word addresses of the element to access.

Turning now to FIG. 9, a computer system 200 including microprocessor 10is shown. Computer system 200 further includes a bus bridge 202, a mainmemory 204, and a plurality of input/output (I/O) devices 206A-206N.Plurality of I/O devices 206A-206N will be collectively referred to asI/O devices 206. Microprocessor 10, bus bridge 202, and main memory 204are coupled to a system bus 208. I/O devices 206 are coupled to an I/Obus 210 for communication with bus bridge 202.

Bus bridge 202 is provided to assist in communications between I/Odevices 206 and devices coupled to system bus 208. I/O devices 206typically require longer bus clock cycles than microprocessor 10 andother devices coupled to system bus 208. Therefore, bus bridge 202provides a buffer between system bus 208 and input/output bus 210.Additionally, bus bridge 202 translates transactions from one busprotocol to another. In one embodiment, input/output bus 210 is anEnhanced Industry Standard Architecture (EISA) bus and bus bridge 202translates from the system bus protocol to the EISA bus protocol. Inanother embodiment, input/output bus 210 is a Peripheral ComponentInterconnect (PCI) bus and bus bridge 202 translates from the system busprotocol to the PCI bus protocol. It is noted that many variations ofsystem bus protocols exist. Microprocessor 10 may employ any suitablesystem bus protocol.

I/O devices 206 provide an interface between computer system 200 andother devices external to the computer system. Exemplary I/O devicesinclude a modem, a serial or parallel port, a sound card, etc. I/Odevices 206 may also be referred to as peripheral devices. Main memory204 stores data and instructions for use by microprocessor 10. In oneembodiment, main memory 204 includes at least one Dynamic Random AccessMemory (DRAM) and a DRAM memory controller.

It is noted that although computer system 200 as shown in FIG. 9includes one bus bridge 202, other embodiments of computer system 200may include multiple bus bridges 202 for translating to multipledissimilar or similar I/O bus protocols. Still further, a cache memoryfor enhancing the performance of computer system 200 by storinginstructions and data referenced by microprocessor 10 in a faster memorystorage may be included. The cache memory may be inserted betweenmicroprocessor 10 and system bus 208, or may reside on system bus 208 ina "lookaside" configuration.

Although the x86 microprocessor architecture and instruction set havebeen used as a specific example herein, it is noted that the apparatusand method described herein may be applicable to any microprocessorwhich employs model specific registers. Such embodiments arecontemplated.

It is still further noted that the present discussion may refer to theassertion of various signals. As used herein, a signal is "asserted" ifit conveys a value indicative of a particular condition. Conversely, asignal is "deasserted" if it conveys a value indicative of a lack of aparticular condition. A signal may be defined to be asserted when itconveys a logical 0 value or, conversely, when it conveys a logical 0value. Additionally, various values have been described as beingdiscarded in the above discussion. A value may be discarded in a numberof manners, but generally involves modifying the value such that it isignored by logic circuitry which receives the value. For example, if thevalue comprises a bit, the logic state of the value may be inverted todiscard the value. If the value is an n-bit value, 1 of the n-bitencodings may indicate that the value is invalid. Setting the value tothe invalid encoding causes the value to be discarded. Additionally, ann-bit value may include a valid bit indicative, when set, that the n-bitvalue is valid. Resetting the valid bit may comprise discarding thevalue. Other methods of discarding a value may be used as well.

Table 1 below indicates fast path, double dispatch, and MROMinstructions for one embodiment of microprocessor 10 employing the x86instruction set:

                  TABLE 1                                                         ______________________________________                                        x86 Fast Path, Double Dispatch, and MROM Instructions                         X86 Instruction   Instruction Category                                        ______________________________________                                        AAA               MROM                                                        AAD               MROM                                                        AAM               MROM                                                        AAS               MROM                                                        ADC               fast path                                                   ADD               fast path                                                   AND               fast path                                                   ARPL              MROM                                                        BOUND             MROM                                                        BSF               fast path                                                   BSR               fast path                                                   BSWAP             MROM                                                        BT                fast path                                                   BTC               fast path                                                   BTR               fast path                                                   BTS               fast path                                                   CALL              fast path/double dispatch                                   CBW               fast path                                                   CWDE              fast path                                                   CLC               fast path                                                   CLD               fast path                                                   CLI               MROM                                                        CLTS              MROM                                                        CMC               fast path                                                   CMP               fast path                                                   CMPS              MROM                                                        CMPSB             MROM                                                        CMPSW             MROM                                                        CMPSD             MROM                                                        CMPXCHG           MROM                                                        CMPXCHG8B         MROM                                                        CPUID             MROM                                                        CWD               MROM                                                        CWQ               MROM                                                        DDA               MROM                                                        DAS               MROM                                                        DEC               fast path                                                   DIV               MROM                                                        ENTER             MROM                                                        HLT               MROM                                                        IDIV              MROM                                                        IMUL              double dispatch                                             IN                MROM                                                        INC               fast path                                                   INS               MROM                                                        INSB              MROM                                                        INSW              MROM                                                        INSD              MROM                                                        INT               MROM                                                        INTO              MROM                                                        INVD              MROM                                                        INVLPG            MROM                                                        IRET              MROM                                                        IRETD             MROM                                                        Jcc               fast path                                                   JCXZ              double dispatch                                             JECXZ             double dispatch                                             JMP               fast path                                                   LAHF              fast path                                                   LAR               MROM                                                        LDS               MROM                                                        LES               MROM                                                        LFS               MROM                                                        LGS               MROM                                                        LSS               MROM                                                        LEA               fast path                                                   LEAVE             double dispatch                                             LGDT              MROM                                                        LIDT              MROM                                                        LLDT              MROM                                                        LMSW              MROM                                                        LODS              MROM                                                        LODSB             MROM                                                        LODSW             MROM                                                        LODSD             MROM                                                        LOOP              double dispatch                                             LOOPcond          MROM                                                        LSL               MROM                                                        LTR               MROM                                                        MOV               fast path                                                   MOVCC             fast path                                                   MOV.CR            MROM                                                        MOV.DR            MROM                                                        MOVS              MROM                                                        MOVSB             MROM                                                        MOVSW             MROM                                                        MOVSD             MROM                                                        MOVSX             fast path                                                   MOVZX             fast path                                                   MUL               double dispatch                                             NEG               fast path                                                   NOP               fast path                                                   NOT               fast path                                                   OR                fast path                                                   OUT               MROM                                                        OUTS              MROM                                                        OUTSB             MROM                                                        OUTSW             MROM                                                        OUTSD             MROM                                                        POP               double dispatch                                             POPA              MROM                                                        POPAD             MROM                                                        POPF              MROM                                                        POPFD             MROM                                                        PUSH              fast path/double dispatch                                   PUSHA             MROM                                                        PUSHAD            MROM                                                        PUSHF             fast path                                                   PUSHFD            fast path                                                   RCL               MROM                                                        RCR               MROM                                                        ROL               fast path                                                   ROR               fast path                                                   RDMSR             MROM                                                        REP               MROM                                                        REPE              MROM                                                        REPZ              MROM                                                        REPNE             MROM                                                        REPNZ             MROM                                                        RET               double dispatch                                             RSM               MROM                                                        SAHF              fast path                                                   SAL               fast path                                                   SAR               fast path                                                   SHL               fast path                                                   SHR               fast path                                                   SBB               fast path                                                   SCAS              double dispatch                                             SCASB             MROM                                                        SCASW             MROM                                                        SCASD             MROM                                                        SETcc             fast path                                                   SGDT              MROM                                                        SIDT              MROM                                                        SHLD              MROM                                                        SHRD              MROM                                                        SLDT              MROM                                                        SMSW              MROM                                                        STC               fast path                                                   STD               fast path                                                   STI               MROM                                                        STOS              MROM                                                        STOSB             MROM                                                        STOSW             MROM                                                        STOSD             MROM                                                        STR               MROM                                                        SUB               fast path                                                   TEST              fast path                                                   VERR              MROM                                                        VERW              MROM                                                        WBINVD            MROM                                                        WRMSR             MROM                                                        XADD              MROM                                                        XCHG              MROM                                                        XLAT              fast path                                                   XLATB             fast path                                                   XOR               fast path                                                   ______________________________________                                         Note: Instructions including an SIB byte are also considered double           dispatch instructions.                                                   

It is noted that other aspects regarding superscalar microprocessors maybe found in the following co-pending, commonly assigned patentapplications: "A Line-Oriented Reorder Buffer for a SuperscalarMicroprocessor", Ser. No. 08/690,385 filed Jul. 26, 1996 by Witt, et al.now U.S. Pat. No. 5,878,244; "Linearly Addressable MicroprocessorCache", Ser. No. 08/146,381, filed Oct. 29, 1993 by Witt now U.S. Pat.No. 5,761,691; "Superscalar Microprocessor Including a High PerformanceInstruction Alignment Unit", Ser. No. 08/377,843, filed Jan. 25, 1995 byWitt, et al. now U.S. Pat. No. 5,819,057; "A Way Prediction Structure",Ser. No. 08/522,181, filed Aug. 31, 1995 by Roberts, et al. now U.S.Pat. No. 5,845,323; "A Data Cache Capable of Performing Store Accessesin a Single Clock Cycle", Ser. No. 08/521,627, filed Aug. 31, 1995 byWitt, et al. now U.S. Pat. No. 5,860,104; "A Parallel and ScalableInstruction Scanning Unit", Ser. No. 08/475,400, filed Jun. 7, 1995 byNarayan now U.S. Pat. No. 5,875,315; and "An Apparatus and Method forAligning Variable-Byte Length Instructions to a Plurality of IssuePositions", Ser. No. 08/582,473, filed Jan. 2, 1996 by Narayan, et al.now U.S. Pat. No. 5,822,559. The disclosure of these patent applicationsare incorporated herein by reference in their entirety.

Numerous variations and modifications will become apparent to thoseskilled in the art once the above disclosure is fully appreciated. It isintended that the following claims be interpreted to embrace all suchvariations and modifications.

What is claimed is:
 1. A microprocessor comprising:a plurality of unitsarranged in a pipeline to effect execution of instructions, each of saidplurality of units including at least one of a plurality of resourcesaccessible via execution of an instruction specifying, in an operandfield of said instruction, one of a plurality of special registeraddresses assigned to said plurality of resources; a remote specialregister bus coupled to each of said plurality of units; and a specialregister unit coupled to said remote special register bus, wherein saidspecial register unit is configured to access said one of said pluralityof resources in response to said instruction, said special register unitconfigured to access said one of said plurality of resources using saidremote special register bus to access said one of said plurality ofresources; wherein said each of said plurality of units comprises aremote special register bus interface for interfacing between said oneof said plurality of resources and said remote special register bus. 2.The microprocessor as recited in claim 1 wherein said special registerunit comprises a register file including one or more special registers,wherein said one or more special registers are identified in saidoperand field of said instruction using a second plurality of specialregister addresses separate from said plurality of special registeraddresses.
 3. The microprocessor as recited in claim 1 wherein saidplurality of units include a reorder buffer.
 4. The microprocessor asrecited in claim 1 wherein said plurality of units include a microcodeunit.
 5. The microprocessor as recited in claim 1 wherein said pluralityof units include a cache.
 6. The microprocessor as recited in claim 1further comprises a decode unit coupled to said special register unit,wherein said decode unit is configured to decode said instruction anddetermine that said instruction accesses a special register.
 7. Themicroprocessor as recited in claim 6 further comprising a microcode unitcoupled to said decode unit and an instruction alignment unit coupled tosaid decode unit, wherein said instruction is sourceable from eithersaid microcode unit or said instruction alignment unit.
 8. A method foraccessing a plurality of resources in a microprocessor, the methodcomprising:decoding an instruction coded to access one of said pluralityof resources; transmitting said instruction to a special register unit;determining if said one of said plurality of resources is local orremote; and transmitting, upon a remote special register bus, a commandfrom said special register unit to a second unit including said one ofsaid plurality of resources if said one of said plurality of resourcesis remote.
 9. The method as recited in claim 8 further comprisingreading a local register file within said special register unit if saidone of said plurality of resources is local.
 10. The method as recitedin claim 8 wherein said second unit comprises a reorder buffer.
 11. Themethod as recited in claim 8 wherein said second unit comprises amicrocode unit.
 12. The method as recited in claim 8 wherein said secondunit comprises a cache.
 13. The method as recited in claim 8 whereinsaid decoding comprises decoding a first operand field of saidinstruction.
 14. The method as recited in claim 13 wherein an encodingof said first operand field comprises a pointer indicating that saidoperand is specified in a second operand field of said instruction. 15.The method as recited in claim 14 further comprising assigning aplurality of special register addresses to said plurality of resources.16. The method as recited in claim 15 further comprising coding saidsecond operand field with one of said plurality of special registeraddresses to access a corresponding one of said plurality of resources.17. A computer system comprising:a microprocessor including:a pluralityof units arranged in a pipeline to effect execution of instructions,each of said plurality of units including at least one of a plurality ofresources accessible via execution of an instruction specifying, in anoperand field of said instruction, one of a plurality of specialregister addresses assigned to said plurality of resources; a remotespecial register bus coupled to each of said plurality of units; and aspecial register unit coupled to said remote special register bus,wherein said special register unit is configured to access said one ofsaid plurality of resources in response to said instruction, saidspecial register unit configured to access said one of said plurality ofresources using said remote special register bus to access said one ofsaid plurality of resources; wherein said each of said plurality ofunits comprises a remote special register bus interface for interfacingbetween said one of said plurality of resources and said remote specialregister bus; and an input/output (I/O) device coupled to saidmicroprocessor, wherein said I/O device is configured to communicatebetween said computer system and another computer system to which saidI/O device is coupled.
 18. The computer system as recited in claim 17wherein said I/O device comprises a modem.
 19. A computer systemcomprising:a microprocessor with flexible resource access including:adecode unit configured to decode a first operand field of aninstruction, wherein said first operand field identifies a primaryregister or a pointer to a plurality of special registers; and a specialregister unit coupled to said decode unit wherein if said first operandfield identifies said pointer to said plurality of specialregisters:said decode unit is configured to convey instructioninformation to said special register unit, said special register unit isconfigured to decode a second operand field, and said special registerunit is configured to access a special register identified by saidsecond operand field; and an input/output (I/O) device coupled to saidmicroprocessor, wherein said I/O device is configured to communicatebetween said computer system and another computer system to which saidI/O device is coupled.
 20. The computer system as recited in claim 19wherein said I/O device comprises a modem.